PIC24F MCUs and dsPIC® Digital Signal Controllers (DSCs) support several operating modes for reducing power consumption. These modes include Idle, Doze, Sleep, and, for devices with XLP technology: Deep Sleep. Some devices can be configured to keep the most critical subsystems running in the event of a Vdd failure (Vbat mode).
On most 16-bit MCUs and DSCs the clock source may also be switched at run-time.
Basic Oscillator for 16-bit MCUs and DSCs
The primary mechanism for saving power is manipulation of the system clock. The following is a simplified illustration of the oscillator system for a 16-bit device. (A more detailed description of the oscillator is presented on the 16-bit Oscillator Page).
A device's system clock (Fosc) is set when exiting reset by the configuration bit settings.
Power Saving Modes
- Doze mode slows down Fcy. Doze mode leaves Fp unchanged.
- Idle mode turns off the clock to the CPU (Fcy), but the peripheral clock (Fp) is kept running.
- Sleep mode turns off most of the system oscillator circuit. The Watchdog Timer (WDT) may be left on in sleep mode if it is running from the low power RC oscillator (LPRC). The content of the memory and all registers are maintained in Sleep mode. Sleep mode has a Low Voltage option.
- Low-Voltage Sleep turns off the same oscillator circuits as does Sleep mode. Low-voltage Sleep retains the memory contents using a low power voltage regulator. It will take longer to wake-up from Low-Voltage Sleep than it does from Sleep Mode.
- Deep Sleep mode turns of the oscillator circuit driving the CPU and the peripherals. If enabled, the Deep Sleep Watchdog Timer (DSWDT) and the Real Timer Clock Calendar (RTCC) are kept running from their dedicated ultra-low power oscillators. Deep Sleep can be entered with or without the a retention option. Without the retention option only the contents of two 16-bit registers are retained; all other memory and registers including the Program Counter are lost. Retention mode preserves all registers and memory values. The Deep Sleep modes allow fewer peripherals to initiate a wake-up than do the two other Sleep modes.
- Vbat mode is a hardware based backup system which runs important peripherals iin the event of a failure on Vdd. Vbat does require the installation of a power source ( i.e. a battery) on a specific I/O pin.
- Program controlled Clock Switching allows the system clock source to be changed at runtime. Clock switching will temporarily override the configuration bit settings, allowing another (lower speed) clock source to generate Fosc. Upon each Reset the clock source reverts to the one determined in the configuration bits.
Summary of Power Savng Modes
| Mode | CPU Clock | Peripheral Clock | Memory Contents | Exit Location |
|---|---|---|---|---|
| Doze | Slow | Running | Retained | Next Instruction |
| Idle | Stopped | Running | Retained | Next Instruction |
| Sleep | Stopped | Stopped | Retained | Next Instruction |
| Low Voltage Sleep | Stopped | Stopped | Retained | Next Instruction |
| Deep Sleep (with retention) |
Stopped | Stopped | Retained | Next Instruction |
| Deep Sleep (w/o retention) |
Stopped | Stopped | Two Registers Retained |
Reset Vector |
| Vbat | Stopped | Stopped | Two Registers Retained |
Reset Vector |
| Clock Switching | scaleed down by equal amounts | Retained | Next Instruction | |
