Chip Industry Week In Review

By The SE Staff - 06 Mar, 2026 - Comments: 0

Think tank IAPS' report on AI integrity attacks contends that advanced AI systems must be protected from hidden tampering, backdoors, or unauthorized changes that could alter their behavior or outputs, especially when AI adoption is scaling rapidly, with over 60% of the federal workforce now using AI every day. Geopolitics The U.S. government has drafted new export rules that may give W... » read more

Research Bits: Mar. 3

By Jesse Allen - 03 Mar, 2026 - Comments: 0

Computational electron microscopy Researchers from Cornell University, TSMC, and ASM used electron ptychography for atomic-scale defect inspection of transistors. The computational imaging method uses an extremely precise electron microscope pixel array detector (EMPAD) to collect detailed scattering patterns of electrons after they pass through transistors and compare how the patterns chan... » read more

Chip Industry Technical Paper Roundup: Mar. 3

By Linda Christensen - 03 Mar, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)

By Technical Paper Link - 23 Feb, 2026 - Comments: 0

A new technical paper, "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography," was published by researchers at Cornell University, ASM and TSMC. Abstract "Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale me... » read more

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

By Laura Peters - 23 Feb, 2026 - Comments: 1

Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

Enabling the Industry’s First GPU-Accelerated Manufacturing Platform

By Synopsys - 19 Feb, 2026 - Comments: 0

Discover how modern chip designs are revolutionizing the lithographic process, driving the need for innovative solutions to meet the industry's demand for shorter design cycles. This whitepaper explores the significant role of GPUs in accelerating computational lithography, offering unprecedented speed-ups for EDA tools in chip development. Learn about the collaborative efforts of Synopsys, NVI... » read more

Chip Industry Week In Review

By The SE Staff - 13 Feb, 2026 - Comments: 0

Geopolitics U.S. lawmakers are urging tighter export controls on advanced semiconductor manufacturing equipment (SME) to China, warning existing loopholes threaten national security. "China is working to build domestic SME by exploiting access to U.S. and allied subcomponents required to produce tools," states the letter, which also says better coordination with allies is essential. The U.S.... » read more

Silicon Photonics In The Data Center: What A CMOS Exec Needs To Know

By Geoff Tate - 09 Feb, 2026 - Comments: 0

Silicon Photonics is changing the data center, with the biggest changes still ahead. Figure 1: Google Jupiter Network for multi-thousand Ironwood TPU clusters. Source: Google Refresher for new readers: Data centers contain hundreds or thousands of racks. For example, the Nvidia GB200 NVL72 AI compute/switch rack is about 24 inches wide, about 88 inches high and 42 inches deep. I... » read more

Chip Industry Week in Review

By The SE Staff - 06 Feb, 2026 - Comments: 1

Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

Chip Industry Week In Review

By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections. Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

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Knowledge Centers
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