Blog Review: Mar. 4

By Jesse Allen - 04 Mar, 2026 - Comments: 0

Cadence's Subash Peddu digs into the challenge of balancing performance, power efficiency, SoC layout optimization, and futureproofing when defining SoCs and memory subsystems for tomorrow’s AI accelerators. Siemens' Nicolae Tusinschi suggests that formal verification isn't just about finding bugs, and the ability to achieve mathematical certainty can fundamentally change how hardware desi... » read more

Blog Review: Feb. 25

By Jesse Allen - 25 Feb, 2026 - Comments: 0

Cadence's Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor and CPU-neutral architecture, common system partition guidelines, and a shared vocabulary and set of standards for system-level and interface definitions between chiplets. Synopsys' Scott Knowlton explains why LPDDR6 represents a big step forward in memory management c... » read more

Leading At Light Speed: What Makes Photonics Leadership Different

By Jan-Bart Smits - 19 Feb, 2026 - Comments: 0

By Jan-Bart Smits and David Harap Every time a transistor switches, it generates heat. Pack enough transistors together and you hit a wall: the chip melts before it computes. This thermal ceiling is why Splunk notes that "as physical and economic limitations are reached, the pace predicted by Moore's Law is slowing." Light solves this problem. Photons carry information without generating ... » read more

SEMI 2026 U.S. Policy Strategy

By SEMI - 19 Feb, 2026 - Comments: 0

The semiconductor industry continues to serve as the foundation of U.S. technological innovation and economic growth, and it has entered its most decisive phase yet. As geopolitical competition intensifies and policy frameworks evolve, 2026 will push the United States to sustain its leadership in semiconductor design, manufacturing, and innovation amid growing alliances and accelerating competi... » read more

Blog Review: Feb. 18

By Jesse Allen - 18 Feb, 2026 - Comments: 0

Synopsys' Raja Tabet anticipates deployment of an agentic AI workforce within the next 12 to 24 months that can take on different engineering personas, such as a digital implementation agent, a verification agent, or an analog agent, to run experiments in parallel, generate and triage tests, and propose fixes. Cadence's Reela Samuel dives into power usage effectiveness in data centers and wh... » read more

Chip Industry Week In Review

By The SE Staff - 13 Feb, 2026 - Comments: 0

Geopolitics U.S. lawmakers are urging tighter export controls on advanced semiconductor manufacturing equipment (SME) to China, warning existing loopholes threaten national security. "China is working to build domestic SME by exploiting access to U.S. and allied subcomponents required to produce tools," states the letter, which also says better coordination with allies is essential. The U.S.... » read more

Blog Review: Feb. 4

By Jesse Allen - 04 Feb, 2026 - Comments: 0

Siemens' Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Cadence's Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability mo... » read more

Chip Industry Week In Review

By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections. Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

Blog Review: Jan. 28

By Jesse Allen - 28 Jan, 2026 - Comments: 0

Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

Chip Industry Week In Review

By The SE Staff - 23 Jan, 2026 - Comments: 0

TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

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Knowledge Centers
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HBM Leads The Way To Defect-Free Bumps

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Chiplet Fundamentals For Engineers: eBook

A 65-page in-depth research report on the next phase of device scaling.

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Chip Industry Week in Review

Memory chip shortages prompt price increases; Israeli chip foundry; 2 acquisitions; Baidu's AI chips; IBM's new quantum processor; GF's GaN push; 3D NAND scaling boosters; U.S. policy recommendations; +$500M in fundings; SiPho and SiGe capacity; EV joint venture.

by The SE Staff

FPGAs Find New Workloads In The High-Speed AI Era

Growing use cases include life science AI, reducing memory and I/O bottlenecks, data prepping, wireless networking, and as insurance for evolving protocols.

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tag: SEMI

Blog Review: Mar. 4

Blog Review: Feb. 25

Leading At Light Speed: What Makes Photonics Leadership Different

SEMI 2026 U.S. Policy Strategy

Blog Review: Feb. 18

Chip Industry Week In Review

Blog Review: Feb. 4

Chip Industry Week In Review

Blog Review: Jan. 28

Chip Industry Week In Review

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