When Cleaning Chips Isn’t Clean Enough

By Gregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Every Atom Now Counts In Advanced Chip Manufacturing

By Gregory Haley - 22 Jan, 2026 - Comments: 0

Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power dens... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies

By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

Data Centers Need High Reliability Semiconductors

By Geoff Tate - 12 Jan, 2026 - Comments: 0

“In the world of designing cars, planes, AI factories … you’ve got to be perfect," said Nvidia CEO Jensen Huang on CNBC last month. "And the reason for this is because there is so much at stake.” Cars and planes need to be extremely reliable because people die if they aren’t. In AI data centers, no one dies when systems fail, but the economic impact is gigantic because Amazon, Goog... » read more

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)

By Technical Paper Link - 01 Jan, 2026 - Comments: 0

A new technical paper titled "Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference" was published by researchers at Rensselaer Polytechnic Institute, ScaleFlux and IBM T.J. Watson Research Center. Abstract "LLM inference is increasingly memory bound, and HBM cost per GB dominates system cost. Current HBM stacks include short on-die ECC that tightens binning, raise... » read more

When To Move To Multi-Die Assemblies

By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Macro Defect Inspection For Mission-Critical Defense, Aerospace, And Advanced R&D Fabs

By Errol Akomer - 18 Dec, 2025 - Comments: 0

Some fabs build consumer chips that sit inside phones and laptops. Others build chips that must survive in orbit, under the Arctic ice, or deep beneath the Earth’s surface. Fabs serving defense, aerospace, national laboratories, and other advanced R&D programs operate under some of the most stringent requirements in the industry. For these facilities, yield is not the only concern. Sec... » read more

Verification and Reliability Methods For RRAM-Based Computing-in-Memory (Univ. of Bremen et al)

By Technical Paper Link - 05 Dec, 2025 - Comments: 0

A new technical paper titled "Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory" was published by researchers at University of Bremen, DFKI GmbH, University of Florida and TU Munich. Abstract "Computing-in-memory (CIM) has gained immense traction owing to the benefits it provides in power, performance, and area. CIM can be don... » read more

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging

By Vineet Pancholi - 20 Nov, 2025 - Comments: 0

The Chiplet Era Has Arrived The floodgates for chiplet-based design have officially opened. Over the past several quarters, manufacturing test flows have been validating 2.5D package architectures, and production volumes are ramping up. These designs promise flexibility and performance, but they also introduce new test sensitivities—electrical, thermal, and mechanical—that challenge tradit... » read more

The Thermal Trap: How Dielectrics Limit Device Performance

By Gregory Haley - 20 Nov, 2025 - Comments: 1

The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

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Knowledge Centers
Entities, people and technologies explored

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Chip Industry Week in Review

Memory chip shortages prompt price increases; Israeli chip foundry; 2 acquisitions; Baidu's AI chips; IBM's new quantum processor; GF's GaN push; 3D NAND scaling boosters; U.S. policy recommendations; +$500M in fundings; SiPho and SiGe capacity; EV joint venture.

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tag: reliability

When Cleaning Chips Isn’t Clean Enough

Every Atom Now Counts In Advanced Chip Manufacturing

Wafer Probe Struggles To Adapt To Multi-Die Assemblies

Data Centers Need High Reliability Semiconductors

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)

When To Move To Multi-Die Assemblies

Macro Defect Inspection For Mission-Critical Defense, Aerospace, And Advanced R&D Fabs

Verification and Reliability Methods For RRAM-Based Computing-in-Memory (Univ. of Bremen et al)

Chiplet Integration and Testing: Key Lessons for Next-Gen Semiconductor Packaging

The Thermal Trap: How Dielectrics Limit Device Performance

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