In-System Test For AI Data Centers

By Ed Sperling - 20 Oct, 2025 - Comments: 0

Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

The Demise Of Static Timing Verification?

By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

Silent Data Corruption

By Ed Sperling - 16 Jul, 2025 - Comments: 0

Everyone expects their compute systems to generate the correct answer. When they don't, it's cause for alarm, because it's not always clear how long the problem has persisted. Even worse, chips and systems are now so complex that it may require a unique sequence of operations to trigger a silent data error, and they may show up only occasionally, and maybe only after months or years of use in t... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)

By Technical Paper Link - 14 May, 2025 - Comments: 0

A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Extending Chip Lifetime With Safer Voltage Scaling

By Eyal Fayneh - 12 Nov, 2024 - Comments: 0

What if your chips lived 20% longer without compromising performance, and even while reducing power consumption? How would it affect your product’s reliability and cost? What would be the effect on your profitability? With the demand for longer-lasting chips growing across industries, designers and reliability engineers face increasing pressure to ensure their products perform correctly fo... » read more

Challenges With Chiplets And Power Delivery

By Ed Sperling - 15 Apr, 2024 - Comments: 0

Chiplets hold the potential to deliver the same PPA benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but ... » read more

Silent Data Corruption Considerations For Advanced Node Designs

By Jyotika Athavale - 12 Mar, 2024 - Comments: 0

Ensuring reliability, availability, and serviceability (RAS) has long been an important consideration for many types of electronic systems, with major implications for chip design. Clearly, military hardware must be very reliable, and servers and automotive systems are also expected to be available constantly. Some amount of failure is inevitable, so being able to repair, avoid, or mitigate fau... » read more

Reducing Power In Data Centers

By Ed Sperling - 16 Jan, 2024 - Comments: 0

The rollout of generative AI, coupled with more data in general, is requiring data centers to run servers harder and longer. That, in turn, is generating more heat and accelerating aging, and to ensure these systems continue working over their projected lifetimes, chipmakers are building extra margin into chips. That increases the amount of energy required to run and cool them, and it can short... » read more

In-Product BTI Aging Sensor For Reliability Screening And Early Detection Of Material At Risk

By PDF Solutions - 09 Jan, 2024 - Comments: 0

We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging a... » read more

Reliability On The Rise In IC Design

By Andre Lange - 14 Sep, 2023 - Comments: 0

Reliability has been an important factor in the semiconductor industry for decades. A closer look reveals three main priorities: In the area of technology development and optimization, the microscopic mechanisms that lead to degradation must be identified and understood before they can be fixed. Microanalytical methods are used here as well as TCAD simulations. If it’s not possible to... » read more

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Knowledge Centers
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tag: aging

In-System Test For AI Data Centers

The Demise Of Static Timing Verification?

Silent Data Corruption

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)

Extending Chip Lifetime With Safer Voltage Scaling

Challenges With Chiplets And Power Delivery

Silent Data Corruption Considerations For Advanced Node Designs

Reducing Power In Data Centers

In-Product BTI Aging Sensor For Reliability Screening And Early Detection Of Material At Risk

Reliability On The Rise In IC Design

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