Tool And Methodology Changes Coming In Fab And Package Automation

By Gregory Haley - 04 Mar, 2026 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss what's changing in semiconductor fabs and packaging houses with Michael Lowman, senior product marketing manager for Data Analytics at Cohu; Aftkhar Aslam, CEO at yieldWerx, Woo Young Han, product marketing director at Onto Innovation; and Lihong Cao, senior director of engineering and technical marketing for ASE. What foll... » read more

Making Hybrid Bonding Better

By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Redefining Backside Metallization: Low‑Temperature Solutions For HDFO And S‑SWIFT Designs

By Dambi Jo - 19 Feb, 2026 - Comments: 0

As chip performance and integration continue to advance, thermal dissipation control has become increasingly critical not only at the wafer fabrication level but also in the packaging industry. For artificial intelligence (AI) and high performance computing (HPC) applications, the industry is gradually shifting toward 2.5D integration. In response to the growing demand, High-Density Fan-Out (HD... » read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges

By Ann Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways • Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems. • As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system. • Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by... » read more

Resistance In Advanced Packages Is Now A System-Level Problem

By Gregory Haley - 10 Feb, 2026 - Comments: 0

Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Chiplets Add More Inspection And Test Steps

By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Six 3D-IC Design Trends That Secure The AI Era

By Pratyush Kamal - 05 Feb, 2026 - Comments: 0

By Pratyush Kamal and Todd Burkholder Greater functionality, performance, and speed are in great demand in pervasive computing, RF, and automotive electronic systems, as well as most everything else. Complexity continues to skyrocket, leading many to say we are officially in the post-Moore’s Law world. In his seminal 1965 paper, “Cramming more components onto integrated circuits,�... » read more

Chiplet Fundamentals For Engineers: eBook

By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier

By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

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tag: advanced packaging

Tool And Methodology Changes Coming In Fab And Package Automation

Making Hybrid Bonding Better

Redefining Backside Metallization: Low‑Temperature Solutions For HDFO And S‑SWIFT Designs

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges

Resistance In Advanced Packages Is Now A System-Level Problem

Chiplets Add More Inspection And Test Steps

Six 3D-IC Design Trends That Secure The AI Era

Chiplet Fundamentals For Engineers: eBook

Multi-Die Assemblies Require More Detailed Test Plan Earlier

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

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