Atomic Operations

This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (€œAtomicOp€) on a target location in Memory Space. The 3 AtomicOps are FetchAdd (Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits.

Endpoints and Root Ports may serve as Requesters for AtomicOps. PCIe Functions with Memory Space BARs as well as all Root Ports may serve as Completers for AtomicOp Requests. Routing elements (Switches, as well as Root Complexes supporting peer-to-peer access between Root Ports) require modification in order to route AtomicOp Requests. AtomicOps are architected for device-to-host, device-to-device, and host-to-device transactions.

Four new bits in the Device Capabilities 2 register enable software to discover specific AtomicOp Completer capabilities in arbitrary PCIe Functions, and AtomicOp routing capability in routing elements. Software discovery of AtomicOp Requester capabilities is not architected, but a new AtomicOp Requester Enable bit in the Device Control 2 register must be set by software in order for a Function to initiate AtomicOp Requests. Software can set a new AtomicOp Egress Blocking bit in routing element Ports as needed to avoid forwarding (“block”) AtomicOp Requests to components that shouldn’t receive them.