...An upcoming open tool for validating, tracing, and debugging RISC-V opcode specifications with CI support. The project is currently in its initial phase of research and exploration, focusing on understanding existing tools and frameworks, studying historical efforts, and identifying gaps to address.

This project builds on significant prior work and contributions that I have made to the riscv-opcodes repository, which forms the foundational groundwork for OpVal.

🔧 Contributions include:

• Refactored and optimized parser logic for opcode ingestion.
• Introduced shared utilities and YAML artifact-generation scripts.
• Enhanced the CI/CD pipeline for faster, more reliable builds.
• Reduced lines of code (LOC) to improve readability and maintainability.
• Optimized the Makefile for streamlined execution and testing.
• Reviewed, fixed, and merged PRs from the wider community.
• Provided best-practice recommendations for structure and maintainability.
• Resolved a multi-extension dependency bug by relocating hinval.vvma and hinval.gvma to rv_svinval_h, ensuring instruction legality when both Svinval and H extensions are used. Also fixed a related parser error affecting output generation.

📌 Notable Pull Requests & Commits:

• Parser Refactor & Logic Simplification
• CI Speed-Up & YAML Loader Enhancements
• Makefile Optimizations
• YAML Cleanup & Validation Fixes
• Test Infrastructure & Coverage
• Build & Parser Adjustments
• Issue Fixes & Robustness Improvements
• All Commits
• PR #297: Split hinval.vvma and hinval.gvma from rv_svinval to rv_svinval_h

These contributions reflect a deep engagement with the RISC-V ecosystem and directly inform the design of OpVal.

As RISC-V adoption increases globally—especially within European initiatives like EPI, CHIPS JU, and RISE—ensuring correctness and trust in custom opcodes, ISA extensions, and trace encodings is critical. OpVal addresses the lack of early validation tooling in the open-source chip toolchain by providing:

• A metadata-based validation engine for opcode definitions.
• Trace log analyzers for verifying architectural correctness.
• CI-friendly integration through command-line tools and GitHub Actions.

OpVal aims to improve developer confidence, reduce ISA-level bugs, and speed up RISC-V processor design and verification pipelines in both academia and industry.

• Validate RISC-V opcode encodings (bit overlap, value fit, syntax correctness)
• Detect argument mismatches in opcode metadata vs. argument lookup tables
• Check representability of constants based on encoding width
• Validate trace logs against expected execution patterns (planned)
• Command-line and CI (GitHub Actions) support
• Modular design to support custom instruction extensions

Current RISC-V tools such as riscv-opcodes, spike, and simulators focus on instruction decoding and execution, but lack formal, early-stage validation of opcode metadata and trace analysis. OpVal fills this gap by:

• Offering standalone validation outside simulation
• Enabling detection of design-time encoding conflicts
• Supporting continuous integration for ISA development workflows

1. Validate opcode additions to riscv-opcodes or other YAML-based metadata repos
2. Trace log checking for debugging and conformance validation
3. Use in academic labs for teaching/custom ISA exploration
4. Support for custom extensions in open hardware startups
5. CI integration to enforce correctness in collaborative development

Note: Installation instructions will be updated after the initial release.

• Python 3.9+ (as earlier versions are depreacted. See more about python versions here
• pyyaml, click (CLI framework), and optional dependencies for trace checking

git clone https://github.com/IIITM-Jay/opval
cd opval
pip install -e .